Caltech Logo

CMS-EE Partners Tech Talk: Accelerate your design development with Stratus High Level Synthesis

Monday, November 13, 2023
12:00pm to 1:00pm
Add to Cal
Annenberg 105
  • Internal Event

Join us for lunch and a discussion with Jared Lee, Director at Cadence Design Systems.

Stratus High Level Syntheses (HLS) allows for rapid micro-architecture exploration to enable designers to meet their Power Performance Area and Schedule goals. In this presentation we will discuss the current state of HLS and it's capabilities.

As a Director at Cadence Design Systems, Jared leads the technical support, sales, and proliferation of the semi-conductor software platforms to current and potential customers across North America and regional accounts. With over 25 years of experience in the semi-conductor IC digital design industry, Jared has a comprehensive knowledge of the solutions ranging from high level synthesis (HLS) to GDSII, including synthesis, formal verification, physical design, and signoff. He is married, with 4 children, and two grandchildren.

For more information, please contact Michelle Lester by phone at (626)395-6363 or by email at [email protected] or visit Next Steps Caltech Student Registration Link.